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Vhdl jobs in rangareddi India

All vhdl jobs found in rangareddi


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Senior Staff Engineer Design
Company: Marvell |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 24 Jul 2026
integration experience Extensive experience in Verilog/VHDL, Spyglass, and quality checks of the implemented RTL for LINT
Senior Member Technical Staff
Company: Siemens |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 24 Jul 2026
. Good to have experience or understanding in: RTL synthesis tool development. System Verilog, VHDL, UPF, DFT, formal
Senior Lead Emulation / Fpga Prototyping Engineer
Company: NXP Semiconductors |

Location: Pune, Maharashtra, India

| Salary: unspecified | Posted: 24 Jul 2026
/Subsystem. Experience with Verilog/System Verilog/VHDL and working knowledge of C/C++ Working knowledge of one more of the
Validation/verification (uvm, Coverage, Agentic), Staff Engineer
Company: Synopsys |

Location: Hyderabad, Telangana, India

| Salary: unspecified | Posted: 24 Jul 2026
of driving coverage closure on complex designs Strong understanding of digital design fundamentals using Verilog, VHDL
Principal Design Engineer
Company: Marvell |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 23 Jul 2026
Extensive experience in Verilog/VHDL, Spyglass, and quality checks of the implemented RTL for LINT and CDC. Hands-on experience
Physical Design Lead
Company: Advanced Micro Devices |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 23 Jul 2026
(PPA) optimization techniques. Good experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design
Soc Integration Engineer
Company: Weekday AI |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 23 Jul 2026
). Proficiency in Verilog, SystemVerilog, or VHDL. Experience using Verdi or equivalent RTL debugging tools. Strong debugging
Amsv Lead
Company: Cyient |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 23 Jul 2026
regression setup Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL-AMS, and optimize testbenches in tools like Xcelium
Amsv Junior Engineer
Company: Cyient |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 23 Jul 2026
and identify root cause for functional mismatch Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL-AMS and capture the
Principal Digital Design Engineer
Company: onsemi |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 23 Jul 2026
is a plus: Knowledge Verilog-A or VHDL-AMS. Experience with embedded CPUs (e.g. ARM Cortex, DSP), AMBA bus protocols (AHB/APB) Experience
Senior Digital Design Engineer
Company: onsemi |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 22 Jul 2026
is a plus: Knowledge Verilog-A or VHDL-AMS. Experience with embedded CPUs (e.g. ARM Cortex, DSP), AMBA bus protocols (AHB/APB) Experience
Fpga Silicon Design Engineer
Company: Altera |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 22 Jul 2026
from architecture, design, validation, to product. - 15+ years of experience in RTL design with Verilog and VHDL. - Familiar
Amsv Senior
Company: Cyient |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 22 Jul 2026
waveform/debug tools and identify root cause for functional mismatch Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL
Soc Integration Engineer
Company: Weekday AI |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 22 Jul 2026
). Proficiency in Verilog, SystemVerilog, or VHDL. Experience using Verdi or equivalent RTL debugging tools. Strong debugging
Asic Verification Eej 2026
Company: Bosch |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 22 Jul 2026
is a desirable but not must.Must have been a part of one or more ASIC/SoC tape outs.Knowledge of VHDL/VERILOG.SPECMAN knowledge
Lead Software Engineer
Company: Cadence Design Systems |

Location: Noida, Uttar Pradesh, India

| Salary: unspecified | Posted: 22 Jul 2026
and algorithms. Knowledge of Verilog, VHDL and Qt is a plus. We’re doing work that matters. Help us solve what others can’t.
High Speed Digital Design Engineer
Company: Thales |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 22 Jul 2026
and ability. VHDL coding, Timing analysis Mastering of electronic simulation and design software (Cadence, Allegro, ANSYS, PSPICE
Asic Verification Eej 2026
Company: Bosch |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 22 Jul 2026
is a desirable but not must.Must have been a part of one or more ASIC/SoC tape outs.Knowledge of VHDL/VERILOG.SPECMAN knowledge
High Speed Digital Design Engineer
Company: Thales |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 22 Jul 2026
and ability. VHDL coding, Timing analysis Mastering of electronic simulation and design software (Cadence, Allegro, ANSYS, PSPICE
Risc V Cpu Design -staff Engineer
Company: Qualcomm |

Location: Bangalore, Karnataka, India

| Salary: unspecified | Posted: 22 Jul 2026
, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging
Vhdl jobs in India