Vhdl jobs in bangalore India
50 vhdl jobs found in bangalore: showing 1 - 50
Cybersecurity Analyst — Semiconductor Ip
Company: Synopsys |
. Either path is sufficient. Ability to read and discuss RTL (Verilog, SystemVerilog, or VHDL), architecture, interfacesLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 22 Oct 2026
Fpga Verification
Company: Weekday AI |
architectures using VHDL / Verilog / SystemVerilog. Deep structural and architectural familiarity with high-density AMD (XilinxLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 21 Oct 2026
Fpga Verification
Company: Weekday AI |
of complex FPGAs. Expert-level RTL development and advanced constrained-random verification architectures using VHDL / VerilogLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 21 Oct 2026
Digital Ic Design Engineer
Company: Texas Instruments |
. Hands on experience in RTL coding. Experience with Verilog/VHDL/System Verilog language. Should be good knowledge on lintLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 21 Oct 2026
Ams Verification Engineer
Company: Skyworks |
data protocols (I2C, UART, SPI, MIPI) - Experience with digital design/verification languages and tools (Verilog, VHDLLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 19 Oct 2026
Ams Verification Engineer
Company: Skyworks |
data protocols (I2C, UART, SPI, MIPI) - Experience with digital design/verification languages and tools (Verilog, VHDLLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 19 Oct 2026
Analog Design Engineer
Company: Skyworks |
(Verilog, VHDL, SystemVerilog, synthesis, etc.) Understanding of analog behavioral modeling techniques (VerilogA, VerilogAMSLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 18 Oct 2026
Analog Design Engineer
Company: Skyworks |
) Experience with digital design/verification languages and tools (Verilog, VHDL, SystemVerilog, synthesis, etc.) UnderstandingLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 18 Oct 2026
Electrical Engineer 1
Company: Skyworks |
) Experience with digital design/verification languages and tools (Verilog, VHDL, SystemVerilog, synthesis, etc.) UnderstandingLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 18 Oct 2026
Dft Senior Engineer
Company: Quest Global |
layouts is essential Programming and Scripting: Proficiency in Verilog, VHDL, C/C++, and scripting languages for testLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 16 Oct 2026
Senior Applications Engineer (functional Verification)
Company: Synopsys |
questions, reproducing the issue, and staying with it until it makes sense. You know your way around Verilog or VHDL well enough.... Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals. Proven experienceLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 15 Oct 2026
Technical Lead I - Vlsi
Company: UST |
Responsibilities: Design and develop RTL using Verilog/SystemVerilog/VHDL for FPGA-based applications. Perform FPGA synthesis, placeLocation: Hyderabad, Telangana - Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 14 Oct 2026
Silicon Soc Integration Design Lead, Google Cloud
Company: Google |
practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel. 5 yearsLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 09 Oct 2026
Fpga Prototyping Applications Engineer
Company: Synopsys |
complex ASIC designs and successfully mapping them to FPGA hardware Deep knowledge of digital design fundamentals, VHDLLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 08 Oct 2026
2027 Campus Hire_ Engineer_ Hw
Company: Qualcomm |
processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experienceLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 01 Oct 2026
Senior Lead Engineer - Design Verification
Company: Quest Global |
, CPU, ARM, Graphics (DDR, PCIE, USB) Should have worked on SOC Level / IP Level design using VHDL, Verilog coding RTL... Coding, CDC, Lint, Spyglass. Good in logic design. Expertise in Verilog and / or VHDL is desired. Strong in SV & OOPS IPLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 29 Sep 2026
Technical Lead - Design Verification
Company: Quest Global |
, CPU, ARM, Graphics (DDR, PCIE, USB) Should have worked on SOC Level / IP Level design using VHDL, Verilog coding RTL... Coding, CDC, Lint, Spyglass. Good in logic design. Expertise in Verilog and / or VHDL is desired. Strong in SV & OOPS IPLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 29 Sep 2026
Fpga Design Engineer (aerospace/defense, Bangalore, 4+ Yrs)
Company: Michael Page |
; Master's or PhD is advantageous. HDL: Strong VHDL and/or Verilog front-end design expertise. FPGA & verification toolsLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 28 Sep 2026
Senior Lead Engineer - Fpga
Company: Raytheon Technologies |
Requirements and develop FPGA Design Architecture Re-engineering and obsolescence management for FPGAs. Write VHDL RTL code... and Reviews Expert-level knowledge in VHDL, System Verilog, etc. Hands on experience in designing with MPSOC and/or RFSOC FPGAsLocation: Yelahanka, Karnataka - Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 24 Sep 2026
Senior Design Verification Engineer
Company: Texas Instruments |
in EE/ECE/CS or related specializations -Excellent debugging skills with SystemVerilog/VHDL/VAMS designsLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 23 Sep 2026
Pd Leadership Role
Company: Advanced Micro Devices |
/Shell/Python scripting, and Verilog/VHDL RTL design and latest use of AI technologies Expert level understanding of EDALocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 23 Sep 2026
Applications Engineering, Sr Engineer
Company: Synopsys |
, and timing closure Strong working knowledge of Verilog, System Verilog, or VHDL, including the ability to read, debugLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 19 Sep 2026
Applications Engineering, Sr Engineer
Company: Synopsys |
, and timing closure Strong working knowledge of Verilog, System Verilog, or VHDL, including the ability to read, debugLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 19 Sep 2026
Applications Engineering, Sr Engineer
Company: Synopsys |
, and timing closure Strong working knowledge of Verilog, System Verilog, or VHDL, including the ability to read, debugLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 19 Sep 2026
Senior Low Power Applications Engineer
Company: Synopsys |
Shell for automation, debugging, and custom flow development Exceptional knowledge of Verilog, VHDL, SystemVerilog RTLLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 17 Sep 2026
Lead Product Engineer
Company: Cadence Design Systems |
. Experience requirement : - Good understanding of HDLs (Verilog, SystemVerilog and/ or VHDL) is MUST - RTL design and synthesisLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 17 Sep 2026
Automotive Functional Safety Staff Engineer - Digital Designware Ip
Company: Synopsys |
26262 ASIL levels, including ASIL D Experience with ISO 26262 Part 5, hardware description languages like Verilog or VHDLLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 16 Sep 2026
Low Power Verification Applications Engineer
Company: Synopsys |
industry-standard LP signoff tools Strong command of VHDL, Verilog, and SystemVerilog RTL, and solid understanding of ASICLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 16 Sep 2026
Constraints Verification Applications Engineer
Company: Synopsys |
, or equivalent industry-standard constraint verification and signoff tools Strong command of VHDL, Verilog, and SystemVerilog RTLLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 15 Sep 2026
Senior Engineer -performance Verification
Company: Ericsson |
programming. Solid skills in RTL debugging issues in simulations of SystemVerilog or VHDL designs. Desired knowledgeLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 15 Sep 2026
Staff Engineer Cpu Ip Design Engineer
Company: GlobalFoundries |
of System Verilog, Verilog and/or VHDL Experience with simulators and waveform debugging tools. Knowledge of logic designLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 08 Sep 2026
Architect, Electrical & Electronics
Company: Danaher |
-based embedded systems for motion control and/or data acquisition, including RTL development using Verilog or VHDLLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 08 Sep 2026
Sr Staff Applications Engineer, Simulation & Debug
Company: Synopsys |
methodologies applied to real designs Strong command of HDL languages including Verilog, VHDL, and SystemVerilog, with solidLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 08 Sep 2026
Senior Digital Design Engineer
Company: onsemi |
What Else You May Bring Experience in some of the following areas is a plus: Knowledge Verilog-A or VHDL-AMS. ExperienceLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 03 Sep 2026
Senior Engineer I Embedded Software Design
Company: Schneider Electric |
, VHDL, Python, or FPGA is essential. Previous involvement in the development of innovative and groundbreaking digitalLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 02 Sep 2026
Field Application Engineer, Verification
Company: Synopsys |
with 3-5 years of hands-on industry experience in ASIC design or verification Strong command of VHDL, VerilogLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 01 Sep 2026
Amsv Senior
Company: Cyient |
waveform/debug tools and identify root cause for functional mismatch Create behavioral models in Verilog-A/AMS, SV-RNM, VHDLLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 01 Sep 2026
Senior Engineer - Fpga Verification (vhdl & Do-254)
Company: Thales |
VHDL to meet the DO-254 excellence. Qualifications Experience: 5 to 8 years in FPGA Verification. Industry: Aerospace... VHDL environment including BFMs/Models and complex test scenarios. Complex Interfaces Validation: ExperienceLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 01 Sep 2026
Technical Lead - Fpga Verification (vhdl, Do-254)
Company: Thales |
: Adoption of latest tools, use of AI. Best Practices: Establish and maintain high-quality coding standards for VHDL... and documentation for DO-254. 2. Operational Execution Environment Development: Directly architect and code critical VHDLLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 31 Aug 2026
Lead Engineer - Rtl Design
Company: Quest Global |
. What You Will Bring: 10+ years of Industry experience. Experience in leading SOC project Experienced in RTL design using VHDL/ VerilogLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 28 Aug 2026
Fpga Silicon Design Engineer
Company: Altera |
from architecture, design, validation, to product. - 15+ years of experience in RTL design with Verilog and VHDL. - FamiliarLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 27 Aug 2026
Fpga Silicon Design Engineer
Company: Altera |
, from architecture, design, validation, to product. - 8+ years of experience in RTL design with Verilog and VHDL. - FamiliarLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 27 Aug 2026
Staff Engineer - Fusa
Company: Synopsys |
(Verilog, VHDL, or SystemVerilog) is an advantage Who You Are You can walk into a design review, spot a safety gap in theLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 25 Aug 2026
Fpga Ip Software Development Engineer
Company: Altera |
and implement clean, efficient, and reusable RTL code using System Verilog, Verilog, or VHDL. IP Integration & Flow Management... using System Verilog, Verilog, or VHDL. Toolchain Expertise: Hands-on proficiency with major FPGA vendor suitesLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 25 Aug 2026
Cpu Physical Design Engineer
Company: Intel |
like Tcl, Perl, and Python for automating physical design workflows. - Experience with Verilog or VHDL for hardwareLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 21 Aug 2026
Senior Staff Engineer
Company: Infineon |
in hardware description languages, including Verilog, SystemVerilog, and VHDL. Strong scripting and programming skills with theLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 20 Aug 2026
Fpga Ip Software Development Engineer
Company: Altera |
and implement clean, efficient, and reusable RTL code using System Verilog, Verilog, or VHDL. IP Integration & Flow Management... using System Verilog, Verilog, or VHDL. Toolchain Expertise: Hands-on proficiency with major FPGA vendor suitesLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 19 Aug 2026
R&d Engineer, Sr Engineer (c/c++, Data Structures, Algorithm, Fpga)
Company: Synopsys |
. Engaging with digital logic design, and applying your knowledge of Verilog/VHDL at the RTL level to enhance hardware/software... logic design, Verilog/VHDL at RTL level, and logic optimization concepts. Experience with FPGA design tools and flowsLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 19 Aug 2026
Soc Architect / Uarchitect
Company: Qualcomm |
and/or performance analysis, simulation, and modelling Languages (Not Mandatory): C/C++, Python, Perl, SystemVerilog, VHDL, VerilogLocation: Bangalore, Karnataka, India
| Salary: unspecified | Date posted: 06 Aug 2026
Pd Architect
Company: Advanced Micro Devices |
(PPA) optimisation techniques. Good experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design