ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years
Job position: ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years, Bangalore, Karnataka
. The recruiter can share more details about compensation for the role in your location during the hiring process......
Job Location: Bangalore, Karnataka, IndiaSalary: unspecified
Company: Cisco Systems
Job posted: 27 Feb 2025
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