Senior Lead Engineer ( RTL/FPGA System Design)
Job position: Senior Lead Engineer ( RTL/FPGA System Design), Bangalore, Karnataka
, IO, Peripherals, DDR, Modem, Bus Protocols) Develop synthesizable models for certain IPs to speed up emulation deployment... to have experience in: Emulation environments for pre-silicon prototyping Designing synthesizable models like bus/jtag transactors......
Job Location: Bangalore, Karnataka, IndiaSalary: unspecified
Company: Qualcomm
Job posted: 18 Apr 2024
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