Mixed Signal ASIC Design - Lead
Job position: Mixed Signal ASIC Design - Lead, Pune, Maharashtra
Verilog, Verilog-A/AMS. Experience with HDL languages Verilog and/or VHDL is desired. Scripting skills: Python, Perl and C......
Job Location: Pune, Maharashtra, IndiaSalary: unspecified
Company: Acz Global Private Limited
Job posted: 04 Apr 2024
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